The present invention pertains generally to clock recovery circuits for supplying a digital clock signal for detecting digital data and specifically to a phase-locked loop circuit for performing that function.
The detection of data communications at a receiver requires the use of a local clock which must be synchronized to that employed at the transmitter for defining the data periods. A common technique presently utilized for effectuating synchronization is to encode the transmitter clock signal in the data so that it can be retrieved from the data signal itself at the receiver. Although there are many well known circuits for recovering a digital clock signal from the data signal, particularly those of the phase-locked loop type, these do not afford the simplicity of design as the present invention together with the level of performance which optimizes maintenance of synchronization once it has been attained.
With the foregoing in mind, it is a primary object of the present invention to provide a new and improved clock recovery circuit for generating a digital clock signal which is synchronized to a data signal.
It is a further object of the present invention to provide such a clock recovery circuit that is simple in design, yet affords a high degree of reliability in maintaining synchronization between the clock and data signals.
It is still a further object of the present invention to provide such a new and improved clock recovery circuit that employs a digitalized phase-locked loop circuit.